In the field of computer technology, there is a continuously growing demand for higher processing and signal conduction capacities in conjunction with a high reliability and flexibility. In the past, chip technology has made a rapid progress with regard to integration density and working speeds or cycle frequencies. With this trend further advancing, problems are coming up for the connection of fast chips. Critical aspects in conjunction with high-speed connections are reliability, cost, on-chip driver size and performance, crosstalk, signal distortions and lack of flexibility in the chip design. Connections between chips by using opto-electronic components and optical waveguides are a solution for many connection problems. Optical connections have an extremely high bandwidth and are comparatively insensitive against crosstalk and other interferences. By using these properties of optical connections, it may become possible to connect high-speed chips with each other by optical channels and to achieve a considerable improvement with regard to connection density, current consumption, interferences and crosstalk.
Usually high-integrated circuits are based on the Si technology. Silicium is however an indirect semiconductor, and the production of efficient optoelectronic components using the Si technology is consequently essentially impossible. Efficient optoelectronic components can however be produced by using the technology of the III/V semiconductors, for instance the GaAs technology, since these semiconductors are often direct semiconductors, consequently emitting and absorbing light with a high efficiency.
For producing integrated circuits, the epitaxial process is commonly employed. If now contacts between layers on the basis of the Si technology and layers on the basis of the technology of the III/V semiconductor are to be made, it is problematic that the lattice constants of the respective materials are different (this also applies to GaP substrates instead of Si substrates). Consequently, during the epitaxial growth of III/V semiconductors on Si (or GaP) substrates, dislocations are created. Such dislocations, however, disturb the function of the complete semiconductor structure to a substantial degree, particularly since the functional layer thicknesses today are on the order of atomic dimensions. In the case of high layer thicknesses, the difference of the lattice constants even leads to bends of the substrate. The reason for this is basically that with high deposition temperatures, an epitaxial growth of III/V semiconductors takes place on Si or GaP semiconductors, however the generation of dislocations begins already at lower deposition temperatures. If then the semiconductor structure cools down to ambient temperature, the differences of the lattice constants caused by the different thermal expansion coefficients will lead to the above stresses and dislocations.
Various approaches exist to eliminate the aforementioned problems. EP 0380815 B1 describes that GaAs layers can be deposited on a Si substrate and form defined microcracks at predetermined positions, thus dislocations of the Si substrate may be avoided, or at least reduced. However, this technology is not suitable for high-integrated circuits because it lacks controllability of microcracks in atomic scales.
EP 0297483 describes a hybrid integrated semiconductor structure, wherein an integrated circuit on the basis of the Si technology is applied to a Si substrate. Further, an optically active element in GaAs technology is provided on the Si substrate. However, an electrical connection between the integrated circuit and the optically active element is not established by a direct contact or by the Si substrate, but rather by an electrical wire connection. This technology is also not suitable for applications in high-integrated circuits.
From the document DE 10355357 it is known, for layer structures with optically active elements on the basis of III/V semiconductors, to compensate dislocations caused by lattice constants, for instance by adaptation layers subjected to tensile stress. By currently known measures, a modeling of electronic properties is also possible, and thus previously inaccessible emission wavelengths become accessible.
US 2004/0135136 A1 describes, a multitude of different III/V semiconductors known in the art, and they are always layers, which are not suitable for application on a Si substrate. Corresponding considerations apply to documents EP 1257026 A2, U.S. Pat. No. 6,233,264 B1, US 2004/0084667 A2, Merz et al., IEE Proc.-Optoelectron. 151(5):346-351 (2004), U.S. Pat. No. 6,072,196, EP 1553670 A2, U.S. Pat. No. 5,825,796, Ishizuka et al., Journal of Crystal Growth 272:760-764 (2004) and US 2004/0161009 A1.
EP 0896406 A2 describes layers of optically active III/V semiconductors on GaP or Si substrates (and others), and these layers contain exclusively In as the III component. In fact, such layers are only suitable for InP substrates and form undesirably many dislocations and faults on Si or GaP substrates. U.S. Pat. No. 5,937,274 describes, in a very general manner, different layers on different substrates.
As a result, the need continues, particularly in the field of high-integrated circuits, to connect subassemblies or layer sequences on the basis of the Si technology and on the basis of the III/V semiconductor monolithically with each other.